Connectivity verification for electronic devices such as printed circuit boards (PCBs) is typically accomplished through either functional simulation, whereby connectivity problems are manifested by failures in functionality, or visual inspection. In the former technique, analysis of failures as being related to connectivity takes time and unnecessarily occupies simulation resources, which may result in project schedule delays. In the event of simulation errors, failures, or unexpected results, for example, an electronic device designer must investigate possible causes, modify a representation of a proposed electronic device used for functional simulation, and re-execute the simulation, possibly several times.
Although the cause of a simulation problem may be as simple as a reversed bus connection or a missing pull-up resistor, current simulation techniques do not provide any sort of automated mechanism to assist in detecting such connectivity issues. Visual inspection of a schematic diagram or other representation of an electronic device used for functional simulation is often the only option for analyzing connectivity. However, this technique is both time consuming and prone to error.
In some cases, simulation models for some components in an electronic device might not exist, and thus verification of connectivity by functional simulation is not possible. Thus, during the design of an electronic device, a designer may potentially be unaware of a connectivity problem until a prototype has been produced and tested.